1. Field of the Invention
The present invention relates to an integrated device having an embedded system in which a memory including a processing device such as a processor is combined in a single chip, a layout method thereof, and a program, and in particular, relates to a power control of the system.
2. Description of Related Art
A power control of a semiconductor integrated circuit is mainly performed such that special hardware for use in a power control such as a power gate and a clock gate is provided and the hardware is controlled to achieve a power optimization.
There is also a technique, such as a cache memory, in which a memory hierarchy is provided and often-accessed data is placed to a nearby hierarchy to enhance the power efficiency. An example of the technique includes the following technique as a power analysis technique of a general processor system.
In this technique, a data access activity at an application software level is profiled on a modeled memory architecture, whereby a logical power optimization is performed according to a cache hit rate or an access status of data on each source code line.